Accessible, FPGA Resource-Optimized Simulation of Multi-Clock Systems in FireSim


Given the complexity of modern systems-on-chip (SoCs), hardware-assisted verification is an integral part of the chip-design process. However, chip designers often need to choose between richly featured but expensive emulation platforms or faster, cheaper, but less debuggable FPGA prototyping solutions. FireSim, an open-source, FPGA-accelerated hardware emulation platform hosted in the public cloud, attempts to accessibly offer the best of both worlds. This article highlights two new FireSim capabilities that help realize this goal: multi-cycle resource optimizations, which can enable an eight-fold increase emulated core count, and FPGA-agnostic support for multi-clock systems. These supplement existing FireSim features which provide a foundation for productive emulation, including a cloud manager to automatically scale out experiments and a rich debug toolkit.

In IEEE Micro, Volume 41 , Issue 4, July-August 2021)